The invention relates to a cell library readable by a computer device having a plurality of pieces of cell data prepared therein which are used in designs of a semiconductor device, and data for designs readable by a computer device which is used in designs of a semiconductor device, and relates to, for example, a technique effective in a case of application to design facilitation for power supply reinforcement.
A technique for the design facilitation of a semiconductor integrated circuit includes a design method of realizing a semiconductor integrated circuit that satisfies a desired logic function using a library of a plurality of functional cells which are previously designed and verified, and a method called, for example, a standard cell method. In many cases, cells normally have logic functions of a simple logic gate, a flip-flop or the like, and geometrically have shapes of which the heights are constant and the widths are variable. A power supply trunk is placed in accordance with a floor plan in advance of the placement of cells, and then the cells are placed. Thereby, various functional circuits are placed in, for example, regions between high-potential power supply routings and low-potential power supply routings. Each high-potential power supply routing and each low-potential power supply routing are connected to the power supply trunk which is previously placed. The functional circuits are supplied with an operating power supply using the high-potential power supply routing and the low-potential power supply routing, and the functional circuits are desirably connected to each other by signal routings for realizing required logic functions between columns or between rows. Required logic simulations or circuit simulations are performed on such an automatic placement and routing result, and functions or characteristics of the system thereof are evaluated. The system is partially corrected in case that required functions or characteristics are not satisfied, and placement and routing are redone from the beginning in case that the correction is inefficient.
Regarding the supply of operating power from the power supply trunk to each high-potential power supply routing and each low-potential power supply routing, at which position the power supply trunk is connected to each high-potential power supply routing and each low-potential power supply routing may be determined in advance in accordance with the power consumption of the functional circuit, or the like. In case that an undesired power supply drop or the like is caused in power supply verification, it maybe possible to cope with the power supply drop by performing automatic placement and routing again, but it is possible to cope therewith manually or by adding a power supply reinforcement process using a separate tool, without changing a layout.
JP-A-9-199600 discloses a power supply reinforcement process for a clock buffer. For example, a technique is disclosed in which functional circuits including a reinforcing power supply routing and a reinforcing ground routing are prepared in advance, as functional circuits such as the clock buffer available to a designer, a functional circuit used in a circuit portion having large power consumption is selected from simulation results, and the selected circuit is replaced with the functional circuit including a reinforcing power supply routing and a reinforcing ground routing. The reinforcing power supply routing draws a current from a high-potential power supply routing of a neighboring column, and the reinforcing ground routing causes a current to flow to a low-potential power supply routing of a neighboring column. Thereby, it is possible to reduce additional man-hours.